1. Field of the Invention
This invention relates to a driving circuit for a liquid crystal display, and more particularly to a shift register employing an amorphous silicon thin film transistor.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) used as a display device for a television or a computer controls light transmittance of a liquid crystal using an electric field. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.
In the liquid crystal display panel, gate lines and data lines are arranged in such a manner to cross each other. The crossing gate lines and data lines define a plurality of liquid crystal cells. The liquid crystal display panel is provided with pixel electrodes and a common electrode for applying an electric field to each liquid crystal cell. Each of the pixel electrodes is connected, via source and drain terminals of a thin film transistor as a switching device, to any one of the data lines. A gate terminal of the thin film transistor is connected to an adjacent gate line.
The driving circuit includes a gate driver for driving the gate lines, and a data driver for driving the data lines. The gate driver sequentially applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel. The data driver applies a video signal to each data line in conjunction with the scanning signal applied to the gate lines. Thus, the LCD controls light transmittance by an electric field applied between the pixel electrode and the common electrode in accordance with a video signal for each liquid crystal cell, thereby displaying a picture.
In such a driving circuit, the gate driver generates a scanning signal for sequentially driving the gate lines using a shift register. The data driver generates a sampling signal for sequentially sampling video signals provided externally by a certain unit using the shift register.
FIG. 1 is a block diagram illustrating a configuration of a related art two-phase shift register.
Referring to FIG. 1, the shift register includes 1st to nth stages connected in cascade. The 1st to nth stages are commonly supplied with first and second clock signals C1 and C2 along with high-level and low-level driving voltages (not shown), and are supplied with a start pulse Vst, which may be an output signal of the previous stage. The 1st stage outputs a first output signal Out1 in response to the start pulse Vst and the first and second clock signals C1 and C2. The 2nd to nth stages output 2nd to nth output signals, respectively, in response to the output signal of the previous stage and the first and second clock signals C1 and C2. The 1st to nth stages have an identical circuit configuration and sequentially shift a signal corresponding to the start pulse Vst. The 1st to nth output signals Out1 to Outn are supplied with a scanning signal for sequentially driving the gate lines of the liquid crystal display panel, or with a sampling signal for sequentially sampling a video signal within the data driver.
FIG. 2 illustrates a detailed circuit configuration of one stage shown in FIG. 1.
In FIG. 2, the stage includes an output buffer part 20 having a pull-up NMOS transistor T5 for outputting a first clock signal C1 to an output line under control of a Q nodes and a pull-down NMOS transistor T6 for outputting a low-level driving voltage VSS under control of a QB node, and a controller part 10 having first to fourth NMOS transistors T1 to T4 for controlling the Q node and the QB node.
The stage is supplied with high-level and low-level voltages VDD and VSS, a start pulse Vst, and a first and second clock signals C1 and C2. Herein, the first clock signal C1 is a signal in which a high-state voltage and a low-state voltage, each having a certain pulse width, are alternately supplied as illustrated in FIG. 3, whereas the second clock signal C2 (not shown) is inverted relative to the first clock signal C1. The start pulse Vst is either supplied externally or from the output signal of the previous stage.
An operation procedure of the stage will be described with reference to driving waveforms illustrated in FIG. 3.
In a period A, a high-state voltage of start pulse Vst is supplied in synchronization with a high-state voltage of the second clock signal C2. The first NMOS transistor T1 is turned on by the high-state voltage of the second clock signal C2 to thereby apply the high-state voltage of the start pulse Vst to the Q node, thereby pre-charging the Q node. The high-stage voltage pre-charged into the Q node turns on the fifth NMOS transistor T5 to thereby apply the low-state voltage of the first clock signal C1 to the output line. The second NMOS transistor T2 is also turned on by the high-state voltage of the second clock signal C2 to thereby apply the high-level driving voltage VDD to the QB node. Then, the high-level driving voltage VDD supplied to the QB node turns on the sixth NMOS transistor T6 to thereby supply a low-level driving voltage VSS. Thus, in period A, the output line of the stage outputs a low-state output signal OUT.
In period B, the first NMOS transistor T1 is turned off by the low-state voltage of the second clock signal C2 to thereby float the Q node into a high state. Thus, the pull-up NMOS transistor T5 maintains a turn-on state. Further, as the high-state voltage is supplied by the first clock signal C1, the floated Q node is boot-strapped by an affect of a parasitic capacitor CGD formed by an overlap between the gate electrode and the drain electrode of the pull-up NMOS transistor T5. Accordingly, the voltage at the Q node is raised further to turn on the pull-up NMOS transistor T5, thereby rapidly supplying the high-state voltage of the first clock signal C1 to the output line. Further, the Q node floated into a high state turns on the fourth NMOS transistor T4, and the high-state first clock signal C1 turns on the third NMOS transistor T3 to supply the low-level driving voltage VSS to the QB node, thereby turning off the pull-down NMOS transistor T6. Thus, in the B period, the output line of the stage outputs a high-state output signal OUT.
In period C, the first NMOS transistor T1 is turned on by the high-state voltage of the second clock signal C2 to supply the low-state voltage of the start pulse Vst to the Q node, thereby turning off the pull-up NMOS transistor T5. Also, the second NMOS transistor T2 is turned on by the high-state voltage of the second clock signal C2 to supply the high-level driving voltage VDD to the QB node, thereby turning on the pull-down NMOS transistor T6 to output the low-level driving voltage VSS to the output line. Also in period C, the third NMOS transistor T3 is turned off by the low-state voltage of the first clock signal C1, and the fourth NMOS transistor T4 is turned off by the low-state voltage of the Q node, thereby keeping the high-level driving voltage VDD at the QB node. Thus, in the C period, the output line of the stage outputs a low-state output signal OUT.
In period D, the first NMOS transistor T1 is turned off by the low-state voltage of the second clock signal C2 to thereby float the Q node. Further, the second NMOS transistor T2 is turned off by the low-state voltage of the second clock signal C2, and the fourth NMOS transistor T4 is turned off by the Q node floated into a low state, so that the QB node is floated in a high state that is slightly lower than the high-level driving voltage VDD supplied in the previous period C even though the third NMOS transistor T3 is turned on by a high-state voltage of the first clock signal C1. Thus, the pull-down NMOS transistor T6 maintains a turn-on state to thereby output the low-level driving voltage VSS to the output line. As a result, in period D, the output line of the stage outputs a low-state output signal OUT.
In the remaining periods, the C and D periods are alternately repeated, so that the output signal OUT of the stage continuously maintains a low state.
There have been efforts to integrate the shift register into the liquid crystal display panel using an amorphous silicon thin flm transistor. However, the amorphous silicon thin film transistor may not function properly due to bias stress when a direct current voltage DV is continuously supplied to the thin film transistor's gate terminal.
For example, in the related art shift register, a high-level driving voltage VDD is applied to the QB node, which is, the gate node of the pull-down NMOS transistor T6, providing a direct current voltage during a majority of periods (i.e., during the remaining period excluding the A and B periods when the Q node becomes a high state) as can be seen in FIG. 3. Persistent direct current voltage on the gate of pull-down NMOS transistor T6 causes a gate bias stress on the transistor, which changes the transistor's threshold voltage Vzh. In this case, a minimum voltage applied to the QB node for the purpose of keeping the Q node at the turn-off voltage is referred to as a clamping voltage, which needs to be more than a certain voltage level. However, a change of threshold voltage Vth in pull-down NMOS transistor T6 due to the gate bias stress reduces the clamping voltage applied to the QB node (i.e., an applied voltage—Vth). Therefore, a problem arises in that an erroneous operation of the shift register, such as a multiple output generation, occurs below a certain voltage on the QB node.